Iterated Timing Analysis and SPLICE 1 bY Rewe A Saleh June 1983

Abettact SPLICE1 is a mixed-mode simulation program for large-scale integrated circuits. It performs concurrent electrical and logic simulation using event-driven selective-trace techniques. The electrical analysis uses a new algorithm , called Iterated Timing Analysis (ITA), which performs accurate electrical waveform analysis much faster than SPICEZ. The logic analysis features a new MOS-oriented state model and a fanout dependent delay model, and handles bidirectional transfer gates in a consistent manner. This report describes the new algorithms and the details of the implementation in SPWCEl.6. Program performance characteristics and a number of simulation results are also included.